Often in the development of devices utilizing electronic circuitry there is a requirement for a means of phase synchronizing a regenerated clock signal to a serial time varying signal and a means of easily controlling the response and performance characteristics of the phase synchronizing means.
Such phase synchronizing means are required in a number of digital circuits such as, for example, a received clock recovery system for the reception of serial bi-level data and digital phase-locked loop (DPLL) for use in frequency multipliers, signal synchronizers, and clock regenerators.
In the past, various means for providing phase synchronization have been used, such as for example, phase-locked loops utilizing an electronic phase detector, analog filter, voltage controlled oscillator and programmable divide by N counters. The main disadvantage of this type of circuit is that in order to change the circuit performance charactertic, certain components must be replaced by different values or other components. Circuit complexity is another big disadvantage, along with component parameter deviations.
Also involved are pre-settable counters which are operated at a specified frequency and whose count is pre-set by input signal transitions. The major disadvantages of this type are circuit complexity and the difficulty in changing the performance characteristics which usually require circuit hardware changes.